With the advancement in serial transmission technologies, interfaces based on serial protocols are becoming more and more popular. The main advantages of a serial interface is the use of fewer signal pins, reduced power, longer transmission distances, and the ability to implement higher data rates. One of the inherent properties of most types of serial communication is the ability to implement features such as scalability. Scalability allows a physical layer device (or PHY) to implement more than one physical link to transmit parts of parallel system data over a transmission medium.
Referring to FIG. 1, a diagram of a system 10 illustrating a conventional physical layer with multiple links is shown. The system 10 is shown having a block 12 and a block 14. The block 12 implements a digital logic and interface circuit. The block 14 implements a serial/deserial (SerDes) circuit. The circuit 12 has an output 20, an output 22, an input 24 and an input 26. The output 20 transmits a number of transmit data lane signals TX_DATA_LANES[n:0]. The output 22 presents a data valid signal TX_DATA_VALID. The input 24 receives a number of receive data lane signals RX_DATA_LANES[n:0]. The input 26 receives a receive clock signal RXCLK[n:0]. The circuit 14 has an input 30 that receives the signal TX_DATA_LANES[n:0], an input 32 that receives the signal TX_DATA_VALID, an output 34 that presents the signal RX_DATA_LANES[n:0] and an output 36 that presents the signal RXCLK[n:0].
One of the problems faced by the designers of the system 10 is to maintain and minimize the lane-to-lane skew between each of the signals TX_DATA_LANES[n:0]. Skew occurs when one signal arrives at a destination sooner than another signal when the signals were intended to arrive at the same time. Skew issues are becoming more and more challenging for layout and/or backend designers as data bit rates are increasing. As newer fabrication processes are advancing towards the denser technologies (i.e., 65 nm and even 45 nm), skew is becoming more challenging to maintain and minimize. Some designs use more than one SerDes interface to establish a multi-lane serial link. A multi-lane SerDes implementation results in even tighter timing requirements for layout tools. Even if timing tools manage to close the timing on these multi-clock domain paths, such systems are sensitive to voltage and temperature variations and therefore prone to instability. Skew issues are common to all multi-lane and/or multi-link transmission systems using SerDes techniques for serial transmission of data.
Referring to FIG. 2, a diagram of a system 10′ is shown. The system 10′ illustrates a number of parallel data paths 50a-50n. A number of bits 52a-52n are shown illustrating the skew of each of the data paths 50a-50n as they leave the circuit 12′. A pattern of bits 0110 is shown on each of the data paths 50a-50n, illustrating an alignment configuration without skew. A second pattern of bits is shown as 54a-54n. The bit patterns 54a-54n are shown as entering the circuit 14′. The bit pattern 54b is shown arriving at the circuit 14′ one clock cycle ahead of the bits 54a. The bit pattern 54c is shown arriving at the circuit 14′ one clock cycle delayed from the bits 54a. The bit pattern 54c is shown delayed by two clock cycles from the bit pattern 54b. The different arrivals of the bit patterns 54a-54n amount to skew. Skew between the paths 50a-50n is more critical on a transmit interface implementing parallel TX data than in a pure serial implementation.
On the receiver side, each receiving data lane TXDATA_0-n is accompanied by a corresponding receive clock TXCLK_0-n. The transmitter lanes TXDATA0-n are usually clocked by a common clock TXCLK[0] but are clocked in at the SerDes by the corresponding TX channel clock. The resulting mis-alignment on the transmit data at the SerDes receiving side can range from a marginal mis-alignment to a more severe mis-alignment depending on the loading on different TX clocks.
It would be desirable to implement a data transmission system that adaptively aligns data path to minimize skew.